This invention relates to the field of integrated circuit fabrication. More particularly, this invention relates to the formation of copper metal electrical interconnects in an integrated circuit.
Consumers continually pressure integrated circuit manufacturers to provide devices that are smaller and faster, so that more operations can be performed in a given amount of time, using fewer devices that occupy a reduced amount of space and generate less heat. For many years, the integrated circuit fabrication industry has been able to provide smaller and faster devices, which tend to double in capacity every eighteen months or so.
However, as integrated circuits become smaller, the challenges of fabricating the devices tend to become greater. Fabrication processes and device configurations that didn""t present any problems at a larger device size tend to resolve into new problems to be overcome as the device size is reduced. For example, in the past there was very little incentive to planarize the various layers from which integrated circuits are fabricated, and which are formed one on top of another. Because the devices themselves were relatively wide, the relatively thin layers that were formed did not present many challenges to overcome in regard to surface topography.
However, as the devices have been reduced in size they have become relatively narrower. Although layer thickness has also generally decreased, the surface topography of an underlying layer tends to create greater problems for the proper formation of the overlying layer to be formed, unless the underlying layer is planarized in some way prior to the formation of the overlying layer.
For example, chemical mechanical polishing can be used to physically and chemically erode the surface of the layer against a polishing pad in a slurry that contains both physically and chemically abrasive materials. Unfortunately, chemical mechanical polishing does not tend to produce surface topographies that are as flat as desired because, although it tends to preferentially remove higher portions of a layer, it also attacks to at least some degree the lower portions of the layer. Thus, even though the higher portions of the layer are removed at a rate that is somewhat greater than that of the lower portions, and hence some planarization does occur, there also tends to be some amount of dishing in the lower portions of the layer, where a greater amount of material is removed than is desired.
As another example of how the reduction in the size of integrated circuits has effected how the integrated circuits are fabricated, in the past the material that was predominantlyxe2x80x94and almost exclusivelyxe2x80x94used for electrical interconnects was aluminum, because it was inexpensive and relatively easy to work with. However, as integrated circuit geometries have been reduced, some of the problems with aluminum have become more pronounced. For example, aluminum electromigration and conductivity have become larger factors. Thus, different materials are substituted for aluminum in various structures. Copper is often used because of its increased conductivity. However, there are issues to overcome with the use of copper as well.
As a specific example, chemical mechanical polishing has typically been used in the formation of copper interconnects, to planarize the deposited copper to the level of preexisting dielectric structures, such as may be formed of low k materials, and over which the copper has been deposited. Unfortunately, not only does the chemical mechanical polishing tend to dish the copper between the dielectric structures, it also tends to erode to some degree the dielectric structures themselves, especially in low density regions of such dielectric structures.
Further, copper tends to more readily diffuse into the surrounding materials that are commonly used during integrated circuit fabrication. Thus, capping layers, such as silicon nitride and silicon carbide are often deposited over a copper layer, to reduce such diffusion into overlying inter metallic dielectric layers. Unfortunately, copper tends to form only a very weak bond with the capping layer of silicon nitride or silicon carbide, and thus electromigration at the copperxe2x80x94capping layer interface continues to be a problem.
What is needed, therefore, is a system whereby a more robust copper interconnect is formed.
The above and other needs are met by a method of forming a metal interconnect in an integrated circuit. A copper layer is formed over dielectric structures on the integrated circuit, where the dielectric structures have an upper level. The copper layer is planarized to be no higher than the upper level of the dielectric structures, without reducing the upper level of the dielectric structures. An electrically conductive capping layer is formed over all of the copper layer, without the capping layer forming over any of the dielectric structures. In this manner, the copper layer is planarized without eroding the level of dielectric structures. Further, the capping layer, which is formed only over the copper layer, reduces the degree of diffusion from the copper layer to an overlying inter metallic dielectric layer, and reduces the electromigration of the copper at the interface with the capping layer.
In various preferred embodiments, the copper is formed using electrochemical deposition. The copper layer is preferably planarized using electrochemical polishing. Preferably, the electrically conductive capping layer is formed using electroless deposition. The dielectric structures are preferably low k materials. The electrically conductive capping layer preferably includes at least one of cobalt and nickel. Preferably, an inter metallic dielectric layer is formed over the electrically conductive capping layer and the dielectric structures. A metal interconnect and an integrated circuit having a metal interconnect formed according to the method are also described.
According to another embodiment of the invention there is described a method of forming a metal interconnect in an integrated circuit. A copper layer is formed over dielectric structures on the integrated circuit. The dielectric structures have an upper level. The copper layer is formed using electrochemical deposition. The copper layer is planarized using electrochemical polishing to be no higher than the upper level of the dielectric structures, which is accomplished without reducing the upper level of the dielectric structures. An electrically conductive capping layer is formed over all of the copper layer using electroless deposition, without the capping layer forming over any of the dielectric structures.
In various preferred embodiments, the dielectric structures are formed of low k materials. The electrically conductive capping layer is preferably at least one of cobalt and nickel. An inter metallic dielectric layer is preferably formed over the electrically conductive capping layer and the dielectric structures.
According to yet another embodiment of the invention, there is described an integrated circuit with a metal interconnect. A copper layer resides between dielectric structures, where the dielectric structures have an upper level, and the upper level of the dielectric structures is substantially uniform across all of the dielectric structures. The copper layer is no higher than the upper level of the dielectric structures. An electrically conductive capping layer is disposed over all of the copper layer, but not over any of the dielectric structures. In various preferred embodiments, the capping layer is at least partially above the upper level of the dielectric structures, and the electrically conductive capping layer is formed of an alloy of at least one of cobalt and nickel.